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5-to-1 Delay to
Rise Time Ratio |
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a-ddl-41p |
- 8 Pin DIP Package Surface Mount
- Risetime: 20% maximum of total delay (see Table)
- Characteristic Impedance: 50, 100 & 200 Ohms ±10%
- Distortion: 10%
- 5 Equally Spaced Taps
- Total Delay: 5 to 100ns
printer
friendly download |
- Tap Delays: 20% increments standard (other increments
available upon request)
- Temperature Coefficient of Delay: 100ppm/°C
max
- Operating Temperature Range: - 55°C
to +125°C
- Storage Temperature Range:
- 65°C to +130°C
- Dielectric Strength: 50VDC
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Input Pulse Test Condition
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Markings & Dimensions
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Mounting Height |
| Code |
Dimension (Max) |
| A |
.200 (5.08) |
| B |
.250 (6.35) |
| C |
.300 (7.62) |
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Ordering Example:
41P-02512B
Series 41P with 50 nanosecond delay
± 2ns with a Tap Delay of 5ns ± .08ns with a
rise time of 7ns Max and a 100 ohm impedance, with Option B pin
sequence.. |
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Pin Number Sequence (Other pin sequences
available upon request) |
Code
Tap # |
In |
20% |
40% |
60% |
80% |
Out |
GND |
| Std. |
2 |
3 |
4 |
5 |
6 |
7 |
1,8 |
| A |
1 |
2 |
3 |
4 |
6 |
7 |
4,8 |
| B |
1 |
7 |
3 |
6 |
4 |
5 |
8 |
| C |
7 |
2 |
6 |
3 |
5 |
4 |
1,8 |
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