40P Series 8 Pin Dual-In-Line Passive Delay

• 8 Pin Package
• TTL and DTL Compatible
• 5 Equally Spaced Taps
• Total Delay: 5 to 100ns

Electrical Specifications

• Total Delay: 5nS to 100nS (see Table below)
• Tap Delays: 20% increments standard (see Table below)
• Risetime: 20% maximum of Total Delay (see Table below)
• Pulse Attenuation: (see Table below)
• Characteristic Impedance: 50 to 200 Ohms (±10%)
• Distortion: ±10%
• Temperature Coefficient of Delay: 100ppm/°C max.
• Operating Temperature Range: - 55°C to 125°C
• Storage Temperature Range: - 65°C to 130°C
• Dielectric Strength: 50VDC
   

Input Pulse Test Condition
 

• Pulse Voltage:            2.5V
• Pulse Width:               5 x T_d
• Pulse Rise Time:         2nS (10% to 90%)

Ordering Example:
40P-10051A
Series 40P with 100 nanosecond delay  ± 5ns with a Tap Delay of 20ns  ± 1ns with a rise time of 28ns Max and a 50 ohm impedance, with Option A pin sequence.

Part No.

Tap Delay
(nanoseconds)
(± 5% or ± 1nS, whichever is greater)

Rise Time
(T_r)
(nanoseconds)
(Max)