50P Series 14 Pin Single-In-Line Passive Delay

• 14 Pin SIP Package
• Low Attenuation - 5% Max
• 10 Equally Spaced Taps
• Total Delay: 10 to 200ns
• Optional Internal Termination

Electrical Specifications

• Total Delay: 10nS to 200nS (see Table below)

• Tap Delays: 10% increments standard (see Table below)

• Risetime: 20% maximum of Total Delay (see Table below)

• Characteristic Impedance: 50 to 100 Ohms (±10%)

• Distortion: 10% Max

• Temperature Coefficient of Delay: 100ppm/°C max.

• Operating Temperature Range: 0°C to 70°C

• Storage Temperature Range: - 55°C to 125°C
   

Input Pulse Test Condition
 

• Pulse Voltage:            2.5V

• Pulse Width:               5 x T_d

• Pulse Rise Time:         2nS (10% to 90%)

Tap Delay
(nanoseconds)
(± 10% or ± 1nS, whichever is greater, referenced from input)

Rise Time
(T_r)
(nanoseconds)
(Max)